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? 65536 – PCA 0 CPn ?
C8051T610/1/2/3/4/5/6/7
26.3.6. 16-Bit Pulse Width Modulator Mode
A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare mod-
ule defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches
the module contents, the output on CEXn is asserted high; when the 16-bit counter overflows, CEXn is
asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA CCFn
match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the
PCA0CPMn register. For a varying duty cycle, match interrupts should be enabled (ECCFn = 1 AND MATn
= 1) to help synchronize the capture/compare register writes. If the MATn bit is set to 1, the CCFn flag for
the module will be set each time a 16-bit comparator match (rising edge) occurs. The CF flag in PCA0CN
can be used to detect the overflow (falling edge). The duty cycle for 16-Bit PWM Mode is given by
Equation 26.3.
Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
Duty Cycle = -----------------------------------------------------
65536
Equation 26.3. 16-Bit PWM Duty Cycle
Using Equation 26.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is
0.0015% (PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
PCA0CPLn
0
ENB
Reset
Write to
PCA0CPHn
ENB
1
PCA0CPMn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
6 n n n
n
n
PCA0CPHn
PCA0CPLn
1
0 0 x 0
x
Enable
16-bit Comparator
match
S
SET
Q
CEXn
Crossbar
Port I/O
R
CLR
Q
PCA Timebase
PCA0H
PCA0L
Overflow
Figure 26.9. PCA 16-Bit PWM Mode
Rev 1.1
199
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